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3d chips. Imagine current size with 1 million layers. Sure it will start with just a few layers. And many obstacles to be overcome like temp and delay. But one
by holoduke 5y ago
3d chips. Imagine current size with 1 million layers. Sure it will start with just a few layers. And many obstacles to be overcome like temp and delay. But one day our cpus will look like little cubes. Moore's law can continue for at least another 30 years
- cogman10 5y agoCouple of problems. First, how do you cool such a chip? Sure, you could add a bunch of transistors but the thermal costs per transistor will stay the same. Assuming similar design but adding 20 layers, how would you account for your CPU now consuming 600W? Second, The tech doesn't exist. The problem we have is that layering chips today is basically growing crystals in a controlled fashion. Defects in lower layers spoil upper layers. Today that's already a problem (CPUs today have ~7 or 8 layers). Can you imagine the problem of 20 or 30 layers? Who knows, maybe we'll come up with solutions to both problems, but that's a big maybe. My bet is that instead we focus on architecture designs. We revisit old but deemed too expensive concepts like an async CPU.
- eloff 5y agoThis is real, shipping technology. See 3d nand flash cells, see stacked cache and HBM memory. All the usual characters are working on it. Intel, AMD (TSMC), Samsung. Cooling is an issue, but there are solutions.
- cogman10 5y ago3d cells for nand aren't the same as 3d CPU cores. Nand is incredibly simple which makes it possible to do things like 3d cells which would otherwise be more complicated. There's a reason memory can generally beat computational cores to smaller node sizes. It's because highly uniform circuits are much easier to manufacture. A lot of problems present in CPU logic cores (such as cross talk) just aren't present to the same extent in NAND cells.
- duck2 5y agoMaybe stuff like Upmem (many small CPUs embedded into memory) can take off then?
- cogman10 5y agoPossibly, that'd be one of the "major architectural changes" that I mentioned earlier. Things we've simply not tried yet because they are too radically different from the way hardware currently works.
- lovemenot 5y agoSorry to have to ask.Could you please show a Wikipedia-like intro to Upmem? It may be a simple typing problem, but Wikipedia doesn't seem to have it.
- duck2 5y agoI found a previous HN submission about them: https://news.ycombinator.com/item?id=20766283 https://news.ycombinator.com/item?id=20766283
- baybal2 5y ago> Today that's already a problem (CPUs today have ~7 or 8 layers). No, I think x86 passed 14+ layers at least half a decade ago.
- cogman10 5y agoSo I'm behind :D. What I remember is them trying to cut down the layers due to yield issues. Guess it's creeped back up again.
- ClumsyPilot 5y agoThat's a continuation of moore's law, it's the same as having a bigger chip horizontally, or more chips. You can make giant chips but you need giants bank accounts. It does not reduce price per transistor because each layer still has to be manufactured the same way
- eloff 5y agoSort of true, except you can use cheaper process scales for some of the layers. The silicon is not actually the expensive part.