3 ms·

Basically, at the low nanometer range,[a] if you want on-chip DRAM, it’d be a separate die (“chiplet”) connected by the substrate [a]: what’s the upper limit?

Basically, at the low nanometer range,[a] if you want on-chip DRAM, it’d be a separate die (“chiplet”) connected by the substrate [a]: what’s the upper limit? As in, when does it not work anymore? For example, would it work at 100+ nm?

baybal2 5y ago
I am not a specialist, but I think I can guess. First, you need a wafer on which you can make a capacitor, which already means an SOI process, and SOI wafers. The lowest nodes with SOI available to mortals are 40nm, and 14nm on GlobalFoundries, but god knows how one gets GloFo to collaborate on that. Then, you need CMOS device which has enough thermal budget to survive both own, and DRAM creation. Third, I think on-die DRAM will only make sense when it wins over SRAM. DRAM cells cannot physically go smaller than the minimal size of a trench capacitor. I believe at 5-7nm nodes, 6T SRAM will already be smaller than a reasonably fast eDRAM per area. We know that IBM's Z15 is a 14nm FinFet chip, and it has DRAM on board, with them probably somehow doing DRAM first.