Nice project. Reading through some of the gotchas is interesting, though one stood out - the RT related gltich. Having some combinatioral logic control a reset

Nice project. Reading through some of the gotchas is interesting, though one stood out - the RT related gltich. Having some combinatioral logic control a reset is in general a no-no, for exactly this reason, a race can happen and combo logic that starts a (say) a 0 and ends at 0 can toggle to 1 and back to 0 multiple times as its boolean equation revolves and if this signal is ever used to drive an async pin like a reset, its a ticking time bomb. May never happen. May happen only when things heat up, may happen only for some logic transitions, etc. All because delays changing slightly can alter the glitch. The fact it didnt happen on the FPGA may be luck, as the logic gates there (LUTs) can and do glitch as they settle, if more than one is connected. However if this particular piece of logic fit in a single LUT, it may avoid the glitch, though still not guaranteed.