3 ms·
> Now you've turned specific access patterns into "attack attempts", We already have error correction detection available to us and it's in use today. > RAM s
by staticassertion 5y ago
> Now you've turned specific access patterns into "attack attempts",
We already have error correction detection available to us and it's in use today.
> RAM should always hold what was last written to it, under all conditions of software accesses.
OK? That's what anyone who is advocating for ECC is already advocating for. ECC is error correcting up to 1 bit and error detecting up to 2 bits. The goal is to ensure that the property you've described holds.
> It only got created because the RAM companies have forsaken correctness,
This problem exists because... physics. Do you actually have a design for RAM that can match today's cell density while somehow providing perfect isolation? Saying this problem didn't exist 15 years ago is like saying that malware didn't impact the abacus - RAM 15 years ago was designed completely differently, and had considerably lower capabilities in terms of storage and latency.
And for reference, hamming codes (which back ECC) were created in the 1950s for error correction in punch cards. This is not a new problem.
ECC is the existing, obvious solution to this problem, it just wasn't built for this threat - but it's an excellent, proven method for correcting bit flips. Even without being designed to prevent rowhammer it already makes the attack much slower, less likely to succeed, and easier to detect (just monitor for a massive spike in ecc corrections).
Trying to design high density RAM that maintains perfect isolation seems pointless. Improving ECC or ECC-like approaches is likely going to be much more effective.
- beebeepka 5y ago> RAM 15 years ago was designed completely differently, and had considerably lower capabilities in terms of storage and latency. You got that backwards, chief. RAM latencies have increased tremendously over the last 15 years.
- namibj 5y agoActual latency has improved, but clock-relative latency hasn't. So what?
- beebeepka 5y agoNo, actual latencies have been climbing since ddr2. Thanks for the downvote though
- njibhu 5y agoThis article from Crucial probably explains the two arguments: https://www.crucial.com/articles/about-memory/difference-between-speed-and-latency https://www.crucial.com/articles/about-memory/difference-bet... But their conclusion is that practical latency has indeed decreased over the last 15 years.
- beebeepka 5y agoAfter looking at the table, I am ready to swallow my pride. Looks like practical latencies have changed a tiny bit. So me and the person I replied to originally were both wrong
- namibj 5y agoAlso note that practical non-high-capacity DDR4 setups reach 3600 CL16. That's way faster than the 3200 CL22 they gave at the bottom.
- formerly_proven 5y agoYou were wrong about the memory latency¹ increasing, but the memory latency² has increased (substantially) for most systems, while the memory latency³ has indeed decreased. In general, the memory latency¹ has not improved much. Of course, the memory latency⁴ has greatly increased, due to the clock frequency being increased so much to enable the higher bandwidth, while the memory latency¹ stayed mostly the same. [1] as in: access latency of the DRAM [2] as in: how long does a CPU memory read which is _not_ cached take [3] as in: how long does a CPU memory read on average take [4] as in: CL
- staticassertion 5y agoNo, I was right. Not that it matters, feel free to replace latency with bandwidth. Or replace it with nothing and focus on capacity. It's a blip on my point, which is that the architecture has changed considerably to allow for progress in other areas.