They specify timing and when it is followed, RAM should work without fault. But if there are corner cases like this, they should be added to specs. Most likely

They specify timing and when it is followed, RAM should work without fault. But if there are corner cases like this, they should be added to specs. Most likely it would require memory controller to remember last addresses and insert delays if rowhammer attempt is detected. And/or make CPU microoperation scheduler avoid it. No idea how expensive would that be, surely nontrivial.