GALs are in essence ROM with both "halves" programmable (as the address decoding logic can also be implemented by mask or fuse programmable bit array). The end

GALs are in essence ROM with both "halves" programmable (as the address decoding logic can also be implemented by mask or fuse programmable bit array). The end result is that you trade bit of generallity for smaller, cheaper and faster device. Modern FPGAs (and IIRC even many CPLDs, as the line got somewhat blurred) are usually implemented as array of LUTs implemented as normal memory with fixed address decode and not with this PLA/PAL/GAL trick. Hence, "programmable logic is just bunch of ROMs". Of interesting historical note is Connection Machine, which while marketed as "computer", is essentially an FPGA stood on it's head. Each of the thousands of CPUs is in essence FPGA LUT block, whose configuration changes for each microinstruction, while routing is fixed.