> not very RISC but extremely useful.. load and store multiple Who was it that said that R and RISC as a nomenclature was always hogwash. A more apt name would

> not very RISC but extremely useful.. load and store multiple Who was it that said that R and RISC as a nomenclature was always hogwash. A more apt name would be “load-store architecture” Onne random thing I remember about LDM/STM was the earliest rev silicon of the Motorola (now Freescale) ARM based DragonBall (then better named the MX line) was the ARM9 core had a bug where LDM/STM would not work with the cache enabled - which of course was horrible, so we hacked gcc to not emit these instructions as a temporary workaround.