4 ms·

You're right about the implications of Kogge-Stone, but constant factors matter a lot. In fixed width ISAs, you have N decoders and all their work is useful.

You're right about the implications of Kogge-Stone, but constant factors matter a lot. In fixed width ISAs, you have N decoders and all their work is useful. In byte granularity dynamic width ISAs, you have one (partial) decoder per byte of your instruction window. All but N of their decode results are effectively thrown away. That's very wasteful. The only way out I can see is if determining instruction length is extremely cheap. That doesn't really describe x86 though. The other aspect is that if you want to keep things cheap, all this logic is bound to add at least one pipeline stage (because you keep it cheap by splitting instruction decode into a first partial decode that determines instruction length followed by a full decode in the next stage). Making your pipeline ~10% longer is a big drag on performance.

dragontamer 5y ago
> In fixed width ISAs, you have N decoders and all their work is useful. ARM isn't fixed width anymore. AESE + AESMC macro-op fuse into a singular opcode, for example. IIRC, high performance ARM cores are macro-op fusing and/or splitting up opcodes into micro-ops. Its not necessarily a 1-to-1 translation from instructions to opcodes anymore for ARM. But yes, a simpler ISA will have a simpler decoder. But a lot of people seem to think its a huge, possibly asymptoticly huge, advantage. ----------------- > The only way out I can see is if determining instruction length is extremely cheap. That doesn't really describe x86 though. I just described a O(n) work / O(log(n)) latency way of determining instruction length. Proposal: 1. have a "instruction length decoder" on every byte coming in. Because this ONLY determines instruction length and is decidedly not a full decoder, its much cheaper than a real decoder. 2. Once the "instruction length decoders" determine the start-of-instructions, have 4 to 8 complete decoders read instructions starting "magically" in the right spots. That's the key for my proposal. Sure, the Kogge-stone part is a bit more costly, but focus purely on instruction length and you're pretty much set to have a cheap and simple "full decoder" down the line.

dragontamer 5y ago

> In fixed width ISAs, you have N decoders and all their work is useful. ARM isn't fixed width anymore. AESE + AESMC macro-op fuse into a singular opcode, for example. IIRC, high performance ARM cores are macro-op fusing and/or splitting up opcodes into micro-ops. Its not necessarily a 1-to-1 translation from instructions to opcodes anymore for ARM. But yes, a simpler ISA will have a simpler decoder. But a lot of people seem to think its a huge, possibly asymptoticly huge, advantage. ----------------- > The only way out I can see is if determining instruction length is extremely cheap. That doesn't really describe x86 though. I just described a O(n) work / O(log(n)) latency way of determining instruction length. Proposal: 1. have a "instruction length decoder" on every byte coming in. Because this ONLY determines instruction length and is decidedly not a full decoder, its much cheaper than a real decoder. 2. Once the "instruction length decoders" determine the start-of-instructions, have 4 to 8 complete decoders read instructions starting "magically" in the right spots. That's the key for my proposal. Sure, the Kogge-stone part is a bit more costly, but focus purely on instruction length and you're pretty much set to have a cheap and simple "full decoder" down the line.