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Here you go. This one combines a high-res die shot with AMD's die breakdown of Zen 2. You'll notice that I understated things significantly. Not only is decode

by hajile 5y ago

Here you go. This one combines a high-res die shot with AMD's die breakdown of Zen 2. You'll notice that I understated things significantly. Not only is decoder bigger than the integer ALUs, but it's more than 2x as big if you don't include the uop cache and around 3x as big if you do! It dwarfs almost every other part of the die except caches and the beast that is load/store https://forums.anandtech.com/threads/annotated-hi-res-core-die-shots-of-zen-1-and-2.2577382/ https://forums.anandtech.com/threads/annotated-hi-res-core-d... Original slides. https://forums.anandtech.com/threads/amds-efforts-involved-in-moving-to-tsmcs-n7-advantages-for-going-with-chiplets-warning-many-images.2577325/ https://forums.anandtech.com/threads/amds-efforts-involved-i...

gchadwick 5y ago
Thanks, my mistake was searching exclusively for Intel micro-architecture. It'd be interesting to see if there are further similar die breakdowns for other micro-architectures around, trawling through conference proceedings likely to yield better results than a quick Google. Just skimming through hot chips as it has a publicly accessible archive (those AMD die breakdowns come from ISSCC which isn't so easily accessible). The decoder is certainly a reasonable fraction of the core area, though as a fraction of total chip area it's still not too much as other units in core are of similar size or larger size (Floating point/SIMD, branch prediction, load/store, L2) plus all of the uncore stuff (L3 in particular). Really we need a similar die shot of a big arm core to compare its decoder size too. Hotchips 2019 has a highlighted die plot of an N1 with different blocks coloured but sadly it doesn't provide a key as to which block is what colour.