> All the experts I listened or read to, they told that instruction set doesn't matter and it is the insignificant thing. The part that matters is branch and da

> All the experts I listened or read to, they told that instruction set doesn't matter and it is the insignificant thing. The part that matters is branch and data prediction, and caching. Also, even intel transforms an instruction into RISC like microinstructions internally. I've heard this before, but I've also seen sources which indicate that x86 instruction decoding is definitely a bottleneck [1-5]. The M1 has a significantly wider pipeline/OoO window/reorder buffer than any other processor, and most sources seem to agree that this is because the simplicity of the ARM ISA allowed Apple to build an 8-wide instruction decoder (as compared to around 4-wide for x86 chips). [1] also mentions that Apple's impressive branch-prediction capabilities are at least partially because ARM's 4-byte-aligned instructions greatly simplify the design of the branch predictor. So yes, it's true that an x86 processor really runs RISC-like uops under the hood. However, the best out-of-order execution pipeline in the world is limited by how far ahead it can see, and that depends on how fast the instruction decoder can feed it instructions. Once again though, I am not a microarchitecture expert. I just read bits of information from people who do know what they're talking about and try to form it into a coherent mental model. If you have knowledge or sources that disagree with me, I would be happy to be proven wrong :) [1]: https://news.ycombinator.com/item?id=25264384 https://news.ycombinator.com/item?id=25264384 [2]: https://www.agner.org/optimize/blog/read.php?i=25 https://www.agner.org/optimize/blog/read.php?i=25 [3]: https://news.ycombinator.com/item?id=26782213 https://news.ycombinator.com/item?id=26782213 [4]: https://www.quora.com/Why-dont-intel-or-AMD-design-an-x86-CPU-capable-of-fetching-over-4-instructions-per-cycle-X86-instructions-generally-encode-quite-a-bit-of-work-so-why-is-skylake-still-limited-to-4-way-Is-it-the-same-utilization https://www.quora.com/Why-dont-intel-or-AMD-design-an-x86-CP... [5]: https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...