3 ms·
Only as long as those workloads are bottlenecked on instruction dispatch, and not memory access. I'm guessing systems based on this chip won't have four to sixt
by twic 5y ago
Only as long as those workloads are bottlenecked on instruction dispatch, and not memory access. I'm guessing systems based on this chip won't have four to sixteen times as much memory bandwidth.
- nine_k 5y ago8-way DDR5 should have merely 4x the bandwidth of 4-way DDR4. OTOH if you run interpreted code, like Python or Ruby, your entire interpreter and bytecode are in L3 cache, but the amount of CPU they spend is large anyway.