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The roadmap code names (lake, cove, etc) are confusing. I have access to roadmaps, etc, via my employer and I can personally only recall the code names for a f
by drewg123 5y ago
The roadmap code names (lake, cove, etc) are confusing. I have access to roadmaps, etc, via my employer and I can personally only recall the code names for a few generations ahead and behind.
The marketing names aren't much better. They sound like a frequent flier program (bronze, silver, gold, platinum) with seemingly meaningless numbers added. You'd think with so many generations and so many configurations, they could come up with a scheme that made sense. I'd name things like:
$GENERATION-$SOCKETS-$CORES-$FREQ
So for a 7th generation Xeon supporting 2 sockets worth of UPI, with 32 cores and a 2.9Ghz clock speed, you'd call it:
Xeon 7-2-32-29
Please Intel? Please?
- pavlov 5y ago"> Xeon 7-2-32-29" Sounds too much like a bingo announcer to me...
- drewg123 5y agoBrings new meaning to the term "silcon lottery" :)
- ksec 5y agoSome of the Codename and Marketing numbers were changed because of the 10nm fiasco. They had to rethink everything ( that stupid (bronze, silver, gold, platinum) thing ) so every code name and product naming sound "new" and at the same time confusing. Something I hope Pat Gelsinger will change it back to his Intel's days.
- nine_k 5y agoThere are many important parameters that are not reflected in this scheme: cache sizes, supported memory timings, TDP, core revisions adding minor features and fixing problems, etc. Not every combination of them makes sense, too. So I suppose some kind of opaque numbering, like "I7400" is shortest. I wish they adopted some position-coded scheme which would be easier to decipher, though. Something like architecture-revision-cores-sockets-cache-RAM-frequently-TDP kind, one letter each. Some Intel KCG2MDTM which would be hard to pronounce, but easy to look up, and easy to compare.
- drewg123 5y agoSome of those, like memory timings, are pure bullshit that they came up with to segment the market when they had no competition. No other vendor limits memory timings. They should just get rid of that. Sorry.. you hit on one of my pet peeves :)
- nine_k 5y agoI think that limiting memory timings, like limiting frequency, is more about stability than market segmentation, so it could be framed as honest. Not supporting ECC memory except in "enterprise" versions is pure segmentation. Good thing AMD broke this unwholesome tradition.