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I don't know what i would do with 80 cores. How much cache and memory bandwidth will this thing have?
by twic 5y ago
I don't know what i would do with 80 cores. How much cache and memory bandwidth will this thing have?
- uluyol 5y agoRun lots of VMs and sell them to others... Various hardware costs get more expensive over time, so the fix is to make things bigger to amortize those costs. I think that even big players don't like running big instances (Google, Facebook, etc.) because when you lose a machine you lose a large % of the capacity for a service. Better to run multiple services so each of those lose a small % each.
- 37ef_ced3 5y agoGolden Cove is intended to support many-core AVX-512 deep learning inference, via, for example: https://NN-512.com https://NN-512.com You can easily and efficiently use 80 cores for inference
- derefr 5y agoRun a data warehouse, on a dataset with power-law querying frequency. Most of the cores would read row-tuples from the same hot memory, do a little bit of local streaming transformation/projection to them, and then send them out to a NIC.
- drewg123 5y agoThis is the most exciting part for me: Its going to have A LOT of memory bandwidth, as the article states they will have DDR5 and HBM2E. I think DDR5 should nearly double throughput over DDR4, and HBM2E supposedly is good for 410GB/sec of memory bandwidth [1] This should give more than enough memory bandwidth to double the number of cores. I'm personally excited by the memory bandwidth and PCIe Gen5 more than the number of cores. I'm hoping we can build a single socket 800Gb/s Netflix OCA :) [1] https://www.tomshardware.com/reviews/glossary-hbm-hbm2-high-bandwidth-memory-definition,5889.html https://www.tomshardware.com/reviews/glossary-hbm-hbm2-high-...
- twic 5y agoAh, thanks, i completely overlooked that mention of HBM2E. So one stack of HBM2E can hold 24 GB, accessed at 410 GB/s. And we can have multiple stacks per package - i see lots of diagrams with four stacks. So a plausible scenario is 80 cores with 96 GB and 1640 GB/s of HBM2E. Per core, that's 1.2 GB and 20.5 GB/s. That's ~320 million cache line fills per second. If the clock speed is 4.6 GHz, that's a cache line fill every 15 cycles, or a 64-bit load every 1.8 cycles. That seems pretty good!
- toast0 5y agoDepening on a lot of application specific stuff, the same thing you'd do with between somewhere between four and sixteen 8 core servers.
- twic 5y agoOnly as long as those workloads are bottlenecked on instruction dispatch, and not memory access. I'm guessing systems based on this chip won't have four to sixteen times as much memory bandwidth.
- nine_k 5y ago8-way DDR5 should have merely 4x the bandwidth of 4-way DDR4. OTOH if you run interpreted code, like Python or Ruby, your entire interpreter and bytecode are in L3 cache, but the amount of CPU they spend is large anyway.
- thechao 5y agoWhen I was Intel we used it for a very solid software rasterizer, an extremely good software raytracer, an extraordinarily fast SQL DB implementation, and for HPC.
- gameswithgo 5y agoMotherboards for those kinds of cpus tend to have 8 channels of ram. Plus DDR5 is coming soon. These kinds of cpus also tend to have tons of L3 cache. One obvious use case is cloud servers, where they are running shared hosting or VMs providing many logical servers. Databases and web servers can usually make use of that many cores no problemo.
- RcouF1uZ4gsC 5y ago> I don't know what i would do with 80 cores. These are actually perfect for building large C++ and Rust code bases.