Current chips on latest nodes are hitting limits of copper interconnect. First, copper deposition gets more, and more defect prone at small feature size — "bad

Current chips on latest nodes are hitting limits of copper interconnect. First, copper deposition gets more, and more defect prone at small feature size — "bad fill" Second, even if you get ultra tiny M0, then the contact is rather poor. At such small dimensions the barrier layer that protects silicon from copper might itself stop behaving like a metal, that's why new interconnects go away from copper for M0 to eliminate the barrier layer.