The ISA affects more than just the instruction decoder. For instance, x86 has partial register writes and TSO memory ordering; RISC-V does not have a condition

The ISA affects more than just the instruction decoder. For instance, x86 has partial register writes and TSO memory ordering; RISC-V does not have a condition code register, and has some special rules for the division operation; and so on. However, RISC-V is so minimal that it might be possible to add it as a second ISA to a chip without much effort. On the other hand, it's so minimal that a JIT translator from RISC-V to the native ISA can be a valid alternative (see for instance https://carrv.github.io/2017/papers/clark-rv8-carrv2017.pdf https://carrv.github.io/2017/papers/clark-rv8-carrv2017.pdf).