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Could a chip have two ISAs? If instruction decoding is as minimal as Intel makes it out to be, then it should be able to have two ISAs translating to the same m
by Pet_Ant 5y ago
Could a chip have two ISAs? If instruction decoding is as minimal as Intel makes it out to be, then it should be able to have two ISAs translating to the same microarchitecture, non?
- throwaway4good 5y agoSure. Probably not always practical. But why not? You could also do just in time translation at the os level.
- cesarb 5y agoThe ISA affects more than just the instruction decoder. For instance, x86 has partial register writes and TSO memory ordering; RISC-V does not have a condition code register, and has some special rules for the division operation; and so on. However, RISC-V is so minimal that it might be possible to add it as a second ISA to a chip without much effort. On the other hand, it's so minimal that a JIT translator from RISC-V to the native ISA can be a valid alternative (see for instance https://carrv.github.io/2017/papers/clark-rv8-carrv2017.pdf https://carrv.github.io/2017/papers/clark-rv8-carrv2017.pdf).
- toast0 5y agoDefinitely. Some ARM processors can switch between ARM and Thumb mode for example, and I think I've seen it on different types as well, but not 100% on details; IIRC things like chips that were compatible with 6502 or similar, but had a native mode with more capabilities and a different instruction set. Of course, it helps if the ISAs are at least broadly similar in terms of register space and available operations and memory ordering specifications. And the performance is in the details.