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That's simply wrong. RISC-V is explicitly designed to enable high-end performance. That was literally one of their goals. Of course with the necessary extension
by nickik 5y ago
That's simply wrong. RISC-V is explicitly designed to enable high-end performance. That was literally one of their goals. Of course with the necessary extensions but that is the case on all ISA.
- tyingq 5y agoThe original paper with the goals: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-...
- snvzz 5y agoPlease also link the current version[0], so that people can see whether the goals have changed. [0] https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/ (start with chapter 1 of the unprivileged spec)