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TSMC Claims Breakthrough on 1nm Chip Production
- david-gpu 5y agoGreat news! It sounds like a good opportunity to start using a better metric. Perhaps millions of transistors per square milliliter? Or billions, at this pace.
- 0-_-0 5y agoI prefer "transistors per square micrometer", it's the same as "million transistors per square millimeter" but shorter to write.
- __alexs 5y agoExcept the density can vary hugely for a single process depending on the type of circuit you're building so even measuring that is quite tricky.
- 0-_-0 5y agoAn improved metric is for example the LMC metric, which uses 3 numbers: density of logic (Dₗ), the density of main memory (Dₘ), and the density of the interconnects linking them (Dᶜ). But density is still a fundamental metric: https://news.ycombinator.com/item?id=27219935 https://news.ycombinator.com/item?id=27219935
- mhh__ 5y agohttps://en.wikipedia.org/wiki/Transistor_count#Transistor_density https://en.wikipedia.org/wiki/Transistor_count#Transistor_de... Enjoy. I have had to link this way too many times while discussing transistor density on this site, apparently it's ingrained that the nanometre figures are mostly bullshit, but not where to actually find a real density figure. Of particular note is just how far (Density isn't everything but to 1* it'll do) behind Intel 14nm is.
- deleted 5y ago[deleted]
- magicalhippo 5y agoAt least for us casuals, a "performance metric" ala number of some standard ARM core (with some fixed caches sizes) or similar per unit area could at least be more relatable? Though not sure if this would be useful for those who actually work in the industry, maybe we'll just end up with "TSMC 8600" etc there too.
- Cthulhu_ 5y agoFor us casuals, there should be straight performance metrics + power consumption figures; transistor scale or amounts don't tell that story.
- magicalhippo 5y agoIf you had a standardized core, you should be able to get those figures as well I presume. Again not sure how much sense they make, but yeah.
- tomxor 5y agoYup, but even density is not enough, it's not possible to get enough power into the most densely packed area, and sometimes the highest performance parts need to be lower density - in other words it's also dependent on microarchitecture. We are so very far away from being able to describe chip performance using basic underlying physical metrics.
- pulse7 5y agoTrue, but it is way better than 5nm, 3nm, 1nm and you can not even cross-compare now...
- Hikikomori 5y agoUnless it's strictly defined and is followed by everyone it's going to be just as useless or useful as xnm is today. I mean, different parts of the chip have different density, cache, logic, etc. Should it be some specific part or average for the full chip? What if one architecture has massive caches which are denser than logic areas? What about AMD Zen with chips of different nodes? Or should it just be what the manufacturer states as the maximum possible, even if no chip gets close to that stated number, even in dense areas of the chip?
- pulse7 5y agoOK. Then it should be the "average number of transistors per square micrometer" for a die.
- tomxor 5y agowould a reasonable simplification be average propagation speed per transistor? Originally (in true denard scaling land) 2D feature size implied speed and density (which in turn implied power efficiency)... but now that features are distorting into different shapes, those two things are not necessarily directly correlated any more, so perhaps they should be measured separately. Propagation is the tricky bit because that's where ultimately designs and usable density come into play, but these are only supposed to be rough guides - a few metrics at extremes could be enough, propagation at highest (unrealistic) density, and a density that is possible to continually drive without heat dissipation and power issues.
- miohtama 5y agoMaybe to start counting individual atoms and molecyles in this point.
- tromp 5y agoI suggested transistor area in https://news.ycombinator.com/item?id=27061358 https://news.ycombinator.com/item?id=27061358
- JohnJamesRambo 5y agoThis is my hope. If the next announcement says they’ve achieved 500 picometer I flip my desk.
- mhh__ 5y agoI have a 0nm chip if anyone wants to see it
- emteycz 5y agoI will give you a lot of money if I can see it, but you must give me a lot of money if I can't - do we have a deal?
- kinghtown 5y agonobody wants your unsolicited chip pics
- Imperatorn 5y agoD has it
- Onewildgamer 5y agoI have embedded a 0nm chip in this comment
- dogma1138 5y agoTSMC claims breakthrough in the arbitrary naming of process nodes.
- tyingq 5y ago“We resolved one of the biggest problems in miniaturizing semiconductor devices, the contact resistance between a metal electrode and a monolayer semiconductor material” I'm no expert, but that sounds significant.
- ummonk 5y agoThe real breakthrough would be figuring out what to name the line after the "1nm". They've backed themselves into a corner, running out of odd numbers.
- phlo 5y agoNot too long ago, process nodes were discussed at μm scale. Extrapolating from the past, I think there's a fairly straightforward way [0] to come up with names for the next few increments. [0] https://en.wikipedia.org/wiki/Metric_prefix#List_of_SI_prefixes https://en.wikipedia.org/wiki/Metric_prefix#List_of_SI_prefi...
- Judgmentality 5y agoOr even better, just use angstrom, which is 1/10 of a nanometer. So you go from 1nm to 9Å. Plus it sounds cool and scientific and it's actually not (total) marketing bullshit. https://en.wikipedia.org/wiki/Angstrom https://en.wikipedia.org/wiki/Angstrom
- vanattab 5y agoWhy would a change in the unit of length change the marketing practices of the silicone foundries?
- Judgmentality 5y ago
- marcodiego 5y agoHmmm... 1nm... Ironically this is technically a quantum machine but not a quantum computer.
- Frost1x 5y ago1nm is a mislabel, actual scale is probably closer to 8nm. These used to represent a physical metric and now they're largely marketing terms.
- ben_w 5y agoThat’s true for all semiconductors — they’re inherently making use of Fermi exclusion and discrete energy levels to have a band gap (and, for that matter, the bands on either side of said gap), and by that the means to be able to switch between conductive and nonconductive states.
- picardo 5y agoThe diameter of an atom is between 0.1 to 0.5 nanometers. Does it mean when the researchers build a 0.1nm scale we can't expect to have any more improvements in chip production?
- dogma1138 5y agoNo, since while the size of atoms already comes into play with modern lithography and has been for a while the 1nm is just an arbitrary number. No feature size is really 1nm in any dimension probably not even close. The definition is more or less arbitrary, TSMC could have released a statement that they made a breakthrough in 1574 Zorks Chip Production and it would be just as true. The only thing that really matters here are the actual characteristics of the node in terms of power and density both on their own and in comparison to previous TSMC nodes and competing nodes. It seems that with this specifically the focus was to create as thin layers as possible. Weird shit begins to happen when you have “extreme” geometries or topologies e.g. graphene that has some unique properties when it comes to electrical conductivity due to how electrons move within the lattice. So it seems that the aim here is to exploit similar effects.
- somedude895 5y agoSo what does the 1nm refer to? Is it just a marketing term for an improvement of x from 4nm?
- adrian_b 5y agoPrecisely that. In the beginning, for every doubling of the transistor density, regardless how that was achieved, the marketing size number was divided by about sqrt(2). More recently the relationship between the density improvement ratio and the marketing size seems to be even less quantitative. So they might claim that their process is 4 times denser than in the recent IBM announcement or maybe that it is just twice denser, if they have divided 2 nm from IBM by 1.4 and they have rounded to 1 nm. Similarly, the IBM "2 nm" announcement was probably intended to claim that it is twice denser than the older announcement of the "3 nm" TSMC process.
- danaos 5y agoBetter article: https://news.mit.edu/2021/2d-transistors-microchip-0513 https://news.mit.edu/2021/2d-transistors-microchip-0513
- adrian_b 5y agoYes indeed, thanks for this link. Not only this other source is much more detailed, but it does not contain any word about a "1 nm" TSMC process, which seems to be a pure invention of whoever has written the news at TechPowerup. The discovery of an appropriate material (bismuth) for electrical contacts to MoS2, which is a semiconductor that can be made in monoatomic layers is indeed extremely newsworthy. There is no doubt that this discovery might enable much denser semiconductor devices in the future, but nobody could say today which would be the name of the TSMC manufacturing process when they would decide to switch from silicon to molybdenum disulfide and in which year would that happen. Certainly not in a year or two. Even a prediction of 5 years would be extremely optimistic for any mainstream components like processors. MoS2 might become usable earlier for some special devices, but there are a huge number of problems to solve before becoming usable for logic devices, e.g. the development of some logic gates appropriate for this material. Being able to make CMOS gates does not seem very likely, at least not any time soon.
- adrian_b 5y agoThe abstract and figures of the published paper can be found by searching for: "Ultralow contact resistance between semimetal and monolayer semiconductors"
- dylan604 5y agoThat's exactly what I was about to say
- baybal2 5y agoCurrent chips on latest nodes are hitting limits of copper interconnect. First, copper deposition gets more, and more defect prone at small feature size — "bad fill" Second, even if you get ultra tiny M0, then the contact is rather poor. At such small dimensions the barrier layer that protects silicon from copper might itself stop behaving like a metal, that's why new interconnects go away from copper for M0 to eliminate the barrier layer.
- andy_ppp 5y agoAt what feature size do cosmic rays and such start to become really problematic for these devices. What about longevity - do the materials start to break down over time if they become this small?
- ben_w 5y agoCosmic rays have been a problem for a while and need special processes and enclosures to mitigate. Likewise, the materials already in use do decay after a while; I’m not a material scientist, but my friends who are gave me the impression the current flowing though it has a similar effect as does anodising aluminium. This may have been an oversimplification, or not, I wouldn’t know.
- bruce343434 5y ago> a similar effect as does anodising aluminium Which means... ? Performance degradation? Gates being destroyed long term? Slight decrease at first but then stable performance for years?
- ben_w 5y agoIt means the atoms from one side of a junction of two dissimilar materials end up embedded inside the other, where you probably don’t want them to be. I am not the right person to ask what the failure looks like (this may have been an analogy for my benefit rather than how it actually happens), but at some point it fails.
- woliveirajr 5y agoPerhaps because "IBM Introduces the World’s First 2-nm Node Chip" [0] in the beggining of May ??? There is (not) some discussion here [1] about it. And, of course, 1nm is half of 2nm. [0] https://spectrum.ieee.org/nanoclast/semiconductors/nanotechnology/ibm-introduces-the-worlds-first-2nm-node-chip https://spectrum.ieee.org/nanoclast/semiconductors/nanotechn... [1] https://news.ycombinator.com/item?id=27219924 https://news.ycombinator.com/item?id=27219924