4 ms·
It might not help at all from a density perspective. The IO die has a lot of pads along the edges that can't be shrunk which puts a lower limit on die area. I
by monocasa 6y ago
It might not help at all from a density perspective. The IO die has a lot of pads along the edges that can't be shrunk which puts a lower limit on die area. I wouldn't be surprised if the logic areas in the middle already have a lot of blank space at 14nm. You used to see the same thing with north bridge chips, and that's basically what the IO die is anyway.
- robocat 5y ago> The IO die has a lot of pads along the edges that can't be shrunk which puts a lower limit on die area. Are you just imagining things? This article includes an image of the 14nm die, along with the functional breakdown further down the article: https://www.tomshardware.com/news/amd-64-core-epyc-cpu-die-design-architecture-ryzen-3000 https://www.tomshardware.com/news/amd-64-core-epyc-cpu-die-d...
- monocasa 5y agoI'm not. Your citation shows extremely dense pads in two banks (even before taking power delivery into account which isn't shown in your functional breakdown), and decent amounts of empty space between the logic blocks.
- exmadscientist 5y agoDensity-wise, no, probably not. But you'll get faster SERDES and should be able to improve the internal routers/crossbars, which contain more logic than you'd think. But, yeah, there isn't a lot there. When the higher cost per area is considered (just count the number of bloody masks...) it's probably a net loss.