3 ms·
What makes registers and L1 cache so much more expensive than L2/L3/RAM?
- phonethrowaway 5y agoSRAM? What do you mean by expensive? Size vs speed?
- phonethrowaway 5y agoL1 cache is optimized for speed. You can't make a large L1 cache... the access is too frequent meaning more bandwidth is needed. L1 has many parallel pipelines vs L2 or 3 which are larger caches, respectively, with less pipelining, respectively.
- phonethrowaway 5y agoBigger size means more latency. L1 needs to be fast due to frequent access. Is that what you mean by expensive?