3 ms·
Most RISC and RISC-derived instruction sets are this way. Power ISA also faults if the PC isn't aligned to 32 bits. ARM Thumb encoding makes this a hair more co
by classichasclass 5y ago
Most RISC and RISC-derived instruction sets are this way. Power ISA also faults if the PC isn't aligned to 32 bits. ARM Thumb encoding makes this a hair more complex, but certainly less than x86.