3 ms·
Well the same guy (yes, he is a madman) did another one in Chisel, which is one step removed from Verilog: https://github.com/antonblanchard/chiselwatt https://
by sennight 5y ago
Well the same guy (yes, he is a madman) did another one in Chisel, which is one step removed from Verilog: https://github.com/antonblanchard/chiselwatt https://github.com/antonblanchard/chiselwatt
I don't spend enough time with FPGAs to even pretend to have an educated opinion on HDLs.
- jhallenworld 5y agoYeah, they are semantically equivalent, but I'm more comfortable in Verilog. It used to be that the open source situation for VHDL was not as good, but it's clearly improving.
- deleted 5y ago[deleted]