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Is it written in FORTH? https://en.wikipedia.org/wiki/Open_Firmware https://en.wikipedia.org/wiki/Open_Firmware If you look at one of the earlier x-series ser
by jhallenworld 5y ago
Is it written in FORTH?
https://en.wikipedia.org/wiki/Open_Firmware https://en.wikipedia.org/wiki/Open_Firmware
If you look at one of the earlier x-series servers- x3650-M1 I think, the BMC (IBM calls it an IMM) is daughter board with a PPC 405 chip. The artwork has "Proudly made in North Carolina" with a map of North Carolina in etch. You can just see it in the picture, under the "IBM":
https://admirestore.top/other/ibm-x3650-rsa-telecharger-pilote-33/ https://admirestore.top/other/ibm-x3650-rsa-telecharger-pilo...
Anyway, I wonder if the code is related. I would have thought this all went to Lenovo.
What you really need for an open-source BMC, is one that works with the common Aspeed KVM chips (ARM-based I think, look at AST2300 and above). This would have the nice effect of avoiding having to pay AMI for their BMC code.
Edit: Actually here is the code, it supports Apseed:
https://github.com/openbmc/openbmc https://github.com/openbmc/openbmc
What's new in LibreBMC is the hardware toolchain. Frankly, they should target RISC-V for this. Edit again: it does, using LiteX:
https://github.com/enjoy-digital/litex https://github.com/enjoy-digital/litex
I'm not sure where Power fits in..
- sennight 5y agoThey're replacing openbmc, thankfully - the build system is absolutely ridiculous. The motivation is to escape binary blob ARM world. You know that POWER and RISC-V are competing solutions, right?
- jhallenworld 5y agoWhich soft-core Power are they using? They mention Lattice ECP5, so a fairly small one I assume.
- sennight 5y agoAn OpenPOWER one, likely this with modification: https://github.com/antonblanchard/microwatt https://github.com/antonblanchard/microwatt
- jhallenworld 5y agoMicrowatt looks nice (though I wish it was Verilog), it has a floating point unit which most of the low-end RISC-Vs do not. Also: "Anton Blanchard", Distinguished Engineer: IBM Total Duration 20 yrs 3 mos
- sennight 5y agoWell the same guy (yes, he is a madman) did another one in Chisel, which is one step removed from Verilog: https://github.com/antonblanchard/chiselwatt https://github.com/antonblanchard/chiselwatt I don't spend enough time with FPGAs to even pretend to have an educated opinion on HDLs.
- jhallenworld 5y agoYeah, they are semantically equivalent, but I'm more comfortable in Verilog. It used to be that the open source situation for VHDL was not as good, but it's clearly improving.
- deleted 5y ago[deleted]
- jabl 5y ago> They're replacing openbmc The press release says they're planning to use openbmc. The "LibreBMC" part seems to be about an open HW platform (incl. created with FOSS tools) for running openbmc. Or are you saying openbmc is planning on some major refactoring?
- sennight 5y agoThe statement was "run software from OpenBMC"... so that could mean almost anything - anything except the conclusion to seem to have drawn. My guess would be that it means they'll grab some of the python code and carve up the systemd scripts. I've been living with an openbmc equipped system for a year or so - there is a lot about it that I won't miss, especially the way it handles serial communication.
- amboar 5y ago> there is a lot about it that I won't miss, especially the way it handles serial communication Out of curiosity, what were the issues you had with OpenBMC's serial communication?
- sennight 5y agoIt was eating characters, which is the second worst thing it could do. Digging into the source, I found a really wonky software buffer... which kind of blew my mind - since hardware buffers and flow control exist. I don't remember if that was a case where python was somehow in the pipeline, but that was unfortunately very common in OpenBMC. I also had a lot of trouble getting the thing to honor the most basic settings, like baud rate. But it is harder to confidently place the blame on that one. Is it OpenBMC's fault that the software provides no clue as to where things are going wrong in the serial plumbing? Is it the AST2500's fault that designers are routing every serial line through it and making it impossible to eliminate as the cause while troubleshooting? Is it IBM's fault, because the design of OPAL (OpenPower Abstraction Layer) encourages construction of this kind of Rube Goldberg machine? If anyone from IBM is listening: don't route all your serial lines through the BMC on your reference designs... system implementers will just copy it.
- Teknoman117 5y agoAll I remember about OpenEmbedded/Yocto was trying to wrap my then teenage brain around it a decade or so ago when it was the build system / distribution of choice for Beagleboards (via Angstrom). Ended up going with buildroot instead at the time...
- bfrog 5y agoSeriously, nothing like spending a day building an image in a way documented only to see it blow up and fail, resulting in having to redo the whole thing. Wish Nix were more popular building embedded system images, the tooling is capable of doing everything bitbake and yocto do, with far saner usage.
- gnufx 5y agoI don't know why FORTH would come into it. OpenBMC does a different job to Open Firmware (Sun Openboot v. ILOM). OpenPOWER boots through Linux -- or at least some of it does. What I really need from a BMC is properly-working and secure IPMI. I don't admin them, so I don't know how how the implementation on the AC922s I use holds up, but I've only had poor experience with proprietary BMC software in the past, and there's considerable appeal to being able to fix it. Why should POWER systems use RISC-V rather than their own free cores?