3 ms·

So really Intel would be 100 nm, TSMC 77 nm, and IBM 55 nm, then? Those node names really are fiction.

tromp 6y ago
Yes, if you assume transistor area to be square and take the side length. In defense of existing nomenclature though, feature size originally denoted the size of the smallest distinguishable feature within a transistor, not the entire transistor.
- ta988 6y ago
  And thats what is important because that's the actual physical limit, for lithography and electron flow reasons.
hwillis 6y ago
50, 38.5, and 27.5 nm. The "transistor-y" part is the inner bit, so you don't count the isolation distance between transistors, which still makes up part of the area. To be more specific, one of the things node names have referred to is the M1 (metal 1) half-pitch, or half the center-to-center distance between the metal traces which connect directly (well, almost directly) between transistors. Originally, the closest width you could space those wires was the same as the thinnest width you could make them, since it's basically just a photo negative. If you take the half pitch, that's the width of a wire. The width of that wire was the thinnest electrode you could make between the n and p regions of silicon, so that was your channel length. Over time we have pushed so that the distance between wires is different from the width of the wires, and the regions of silicon are larger than the distances between them, ect. etc. So channel length started to shrink much faster than the wires, and in the 2000s it was less than half of the node name and fully a third of the M1 half-pitch. Since then things got even weirder, and "channel length" doesn't correspond to the changes in performance any more. Since the M1 pitch doesn't track the nodes very well, area density probably won't either. The reason it does so well is probably more to do with the fact that its the other major process goal besides performance- the more transistors you squeeze in, the more chips you get per wafer at a given performance. Foundries ensure the area density keeps increasing as fast as performance, and the difficulty has kept rough pace with performance. It's entirely possible that relative difficulty will change and area density will start to underperform as a metric for performance.

Yes, if you assume transistor area to be square and take the side length. In defense of existing nomenclature though, feature size originally denoted the size of the smallest distinguishable feature within a transistor, not the entire transistor.

ta988 6y ago
And thats what is important because that's the actual physical limit, for lithography and electron flow reasons.

hwillis 6y ago

50, 38.5, and 27.5 nm. The "transistor-y" part is the inner bit, so you don't count the isolation distance between transistors, which still makes up part of the area. To be more specific, one of the things node names have referred to is the M1 (metal 1) half-pitch, or half the center-to-center distance between the metal traces which connect directly (well, almost directly) between transistors. Originally, the closest width you could space those wires was the same as the thinnest width you could make them, since it's basically just a photo negative. If you take the half pitch, that's the width of a wire. The width of that wire was the thinnest electrode you could make between the n and p regions of silicon, so that was your channel length. Over time we have pushed so that the distance between wires is different from the width of the wires, and the regions of silicon are larger than the distances between them, ect. etc. So channel length started to shrink much faster than the wires, and in the 2000s it was less than half of the node name and fully a third of the M1 half-pitch. Since then things got even weirder, and "channel length" doesn't correspond to the changes in performance any more. Since the M1 pitch doesn't track the nodes very well, area density probably won't either. The reason it does so well is probably more to do with the fact that its the other major process goal besides performance- the more transistors you squeeze in, the more chips you get per wafer at a given performance. Foundries ensure the area density keeps increasing as fast as performance, and the difficulty has kept rough pace with performance. It's entirely possible that relative difficulty will change and area density will start to underperform as a metric for performance.