3 ms·
Would achievable SRAM cache size per mm2 work?
by MrBuddyCasino 6y ago
Would achievable SRAM cache size per mm2 work?
- deleted 6y ago[deleted]
- Tuna-Fish 6y agoThat is an important metric, but SRAM scales differently to logic density, and there can be processes where SRAM is proportionally much more or less expensive than some logic. Properly representing transistor density is a very hard problem, to which many different solutions have been proposed. It's just that the solution typically shows the processes of those who proposed it in the best possible light, so there is no industry consensus.
- keanebean86 6y agoHow about making an open source benchmark chip. It could have sram, logic, io, etc. As part of releasing a node, manufacturers would port the benchmark chip.
- tromp 6y agoThey could make it a chip to efficiently solve Cuckatoo32 [1], using 1GB of SRAM (or 0.5GB SRAM and 0.5GB off-chip DRAM) to find cycles in bipartite random graphs with 2^32 edges. [1] https://github.com/tromp/cuckoo https://github.com/tromp/cuckoo
- tomcam 6y agoThat seems kind of brilliant to me.
- syockit 6y agoThat might prove to be a difficult endeavour for foundries that do not design their own chips.