4 ms·
IBM already have a chip with a gigabyte of L3 cache, so maybe that combats the latency in another way
by erk__ 5y ago
IBM already have a chip with a gigabyte of L3 cache, so maybe that combats the latency in another way
- formerly_proven 5y agoReducing average memory read/write latency (as well as increasing bandwidth) is the point of big caches - but, cet. par. bigger caches inherently have higher lookup latency, deeper cache hierarchies increase the latency further and cache sizes are also limited by ISA concerns (4K pages on x86 limit the size of VIPT caches). So a system with a deep cache hierarchy and large caches will perform better on average, but actually going out there and getting bits from main memory will take longer. Not least because the actual, physical latency of DRAM itself improves only very, very slowly, this makes old systems stand up quite well in this particular metric against modern systems.