5 ms·
The table in the article suggests to me that instead of this fictional "feature size", we could use the achievable transistor area as a more meaningful measure
by tromp 6y ago
The table in the article suggests to me that instead of this fictional "feature size", we could use the achievable transistor area as a more meaningful measure of process scale.
IBM achieved 50B transistors in 150mm^2, for a per-transistor area of 3000 nm^2.
TSMC's 5nm process (used by Apple's M1 chip) apparently achieves a transistor area of 5837 nm^2, while Intel's 10nm is lagging at roughly 10000 nm^2.
- iamgopal 6y agoShouldn’t we need to use volume instead of area ?
- tromp 6y agoI think cooling requirements will keep use of the 3rd dimension severely limited in the foreseeable future. Also, the required number of lithographic steps might make it economically infeasible.
- londons_explore 6y agoNAND manages 100+ stacked transistors. Things like processor caches have similarly low average switching rates, so it doesn't seem out of the realm of possibility to see use of the third dimension for logic.
- selectodude 6y agoNAND isn’t ever all being used at the same time and even then it can get very hot. SSD thermal throttling is a genuine issue.
- xxs 6y agoSSD thermal throttle the controller =not= the NAND, itself... which actually doesn't even like to be cold.
- wtallis 6y agoDepends on the drive. Sometimes it really is the NAND getting too hot.
- merb 6y agoif you use the latest drives m.2 pci4, etc. high end the whole thing gets really hot. high end boards thus have heat sinks. keep in mind nand needs to be warm to reach peak perf, but not too warm. the whole heat sinks can reduces the heat by as much as 7°C degree.
- sterlind 6y agoI've heard of proposals to do cooling via microfluidic channels, but the lithographic steps problem seems inevitable. at least unless you can somehow pattern multiple layers at once, which would destroy the feature size.
- dehrmann 6y ago> I think cooling requirements will keep use of the 3rd dimension severely limited in the foreseeable future. It's fun to go look back on old CPU coolers. They started around Pentium-era CPUs, then kept getting bigger. Around 100W TDP, they stopped. I think that's the largest practical air-cooled cooler.
- verall 6y agoA consumer tower (air) cooler can clear 150W on the stock fan and if you stick some 2k-3k rpm push-pull it will probably clear 300W. Fancier vapor chambers and thicker, higher RPM fans can clear up to thousands in server environments.
- pjc50 6y agoThey're still not stacked, as far as I'm aware - still needs to be in a "well" on the substrate.
- Nokinside 6y agoYes. Transistor density is a good measure that translates into something meaningful. It can be compared across different process technologies. Bear in mind that transistor density is not not actually transistor density. Transistor density is weighted number that combines NAND2 transistors/area and scan flip-flops/area. Tr/mm² = 0.6×(NAND2 Tr/mm²) + 0.4×(scan flip-flop/mm²)
- nousermane 6y agoFor anyone wondering why this is done like so instead of literally counting transistors: Transistors with 2,3,.. gates are functionally identical to 2,3,.. transistors connected in series, but take chip area that is only a small fraction larger than 1 "normal" transistor. Counting those as either 1, or as multiple (by number of gates) would skew stats in a less-then-useful way. That is - among other quirks. Ken Shirriff [1] has some excellent articles that touch the topic of what exactly counts as a "transistor". [1] http://www.righto.com/ http://www.righto.com/
- MrBuddyCasino 6y agoWould achievable SRAM cache size per mm2 work?
- deleted 6y ago[deleted]
- Tuna-Fish 6y agoThat is an important metric, but SRAM scales differently to logic density, and there can be processes where SRAM is proportionally much more or less expensive than some logic. Properly representing transistor density is a very hard problem, to which many different solutions have been proposed. It's just that the solution typically shows the processes of those who proposed it in the best possible light, so there is no industry consensus.
- keanebean86 6y ago
- TchoBeer 6y ago>10000 Too many zeroes?
- slfnflctd 6y agoI thought this at first too, but after re-reading it became clear that they're saying IBM's process takes up the least room per transistor on average while Intel's takes up the most. So IBM is actually beating Apple by this metric here, however counter-intuitive that may seem.
- mkl 6y agoIBM's 2nm beating TSMC's 3nm doesn't seem counter-intuitive. If their naming systems are comparable it's exactly what you'd expect.
- slfnflctd 6y agoWell, everyone knows now that the 'X nm' naming doesn't actually mean much when looking at the whole chip, which is why we're talking about transistors per area. Also, Apple has been designing modern chips with massive production volumes for a while, and IBM... hasn't (in fact, they've mostly sold off their former fabrication capabilities). So that's why my expectations were a little different.
- hexane360 6y agoThat makes sense as well. It's not unexpected that a one-off F1 car is faster than a mass-produced Mustang.
- mkl 6y agoNo, Intel's 10nm is a bigger process, lagging behind TSMC's 5nm, so its per-transistor area is bigger.
- TchoBeer 6y agoI see, I was reading the numbers as a density (per nm^2)
- mrfusion 6y agoWow that’s a shocking difference from the 2nm. Who can I trust anymore?
- PhaseLockk 6y agoIn the original naming scheme, 2nm would be the length of the transistor gate, which is the smallest feature on the device, not a dimension of the whole transistor. It's not meaningful to compare 2nm to the area numbers given above.
- fallingknife 6y agoSo really Intel would be 100 nm, TSMC 77 nm, and IBM 55 nm, then? Those node names really are fiction.
- tromp 6y agoYes, if you assume transistor area to be square and take the side length. In defense of existing nomenclature though, feature size originally denoted the size of the smallest distinguishable feature within a transistor, not the entire transistor.
- ta988 6y agoAnd thats what is important because that's the actual physical limit, for lithography and electron flow reasons.
- hwillis 6y ago50, 38.5, and 27.5 nm. The "transistor-y" part is the inner bit, so you don't count the isolation distance between transistors, which still makes up part of the area. To be more specific, one of the things node names have referred to is the M1 (metal 1) half-pitch, or half the center-to-center distance between the metal traces which connect directly (well, almost directly) between transistors. Originally, the closest width you could space those wires was the same as the thinnest width you could make them, since it's basically just a photo negative. If you take the half pitch, that's the width of a wire. The width of that wire was the thinnest electrode you could make between the n and p regions of silicon, so that was your channel length. Over time we have pushed so that the distance between wires is different from the width of the wires, and the regions of silicon are larger than the distances between them, ect. etc. So channel length started to shrink much faster than the wires, and in the 2000s it was less than half of the node name and fully a third of the M1 half-pitch. Since then things got even weirder, and "channel length" doesn't correspond to the changes in performance any more. Since the M1 pitch doesn't track the nodes very well, area density probably won't either. The reason it does so well is probably more to do with the fact that its the other major process goal besides performance- the more transistors you squeeze in, the more chips you get per wafer at a given performance. Foundries ensure the area density keeps increasing as fast as performance, and the difficulty has kept rough pace with performance. It's entirely possible that relative difficulty will change and area density will start to underperform as a metric for performance.
- dorfsmay 6y agoIf somebody wonders what those size actually mean, here are reddit threads with some enlightening answers, from the last time I digged into this: https://old.reddit.com/r/ECE/comments/jxb806/how_big_are_transistors_in_modern_cpu_how_many/ https://old.reddit.com/r/ECE/comments/jxb806/how_big_are_tra... https://old.reddit.com/r/askscience/comments/jwgdld/what_is_the_size_of_transistors_in_5_nm/ https://old.reddit.com/r/askscience/comments/jwgdld/what_is_...
- robocat 6y agoHere's the table: "Peak Quoted Transistor Densities (MTr/mm2)" IBM TSMC Intel Samsung 22nm 16.50 16nm/14nm 28.88 44.67 33.32 10nm 52.51 100.76 51.82 7nm 91.20 237.18* 95.08 5nm 171.30 3nm 292.21* 2nm 333.33 Data from Wikichip, Different Fabs may have different counting methodologies * Estimated Logic Density
- kuprel 6y agoI wonder if these logic densities could be converted into units of nanometers. For example 333 MTr/mm2 is 333 Tr/um2. Then there are effectively sqrt(333) transistors on a side of a square micrometer which comes out to about 1/sqrt(333) * 1000 = 55 nanometers per transistor. Way off from the 2 nanometer feature size
- watersb 6y ago> 55 nanometers per transistor. Way off from the 2 nanometer feature size. Cool. Following along here, I consider that transistors require multiple "features", and these days the more complicated transistor structure has enabled the increase in speed while lowering the power requirements. Power is also now a set of characteristics, the power needed to change transistor state, and the leakage current that remains when the transistor is not switching. Not just a simple NPN junction FET anymore. Then I think about those great microchip analyses on Ken Sheriff's blog. How very different transistor layouts show up in circuit designs. I can only imagine that modern high performance SOC design is even more complex. https://righto.com https://righto.com 55 nanometers per transistor sounds like a useful number to me.
- apatheticonion 6y agoSo does that mean Intel's 10nm products are as good as AMD's 7nm products?
- avs733 6y agoIt is slightly more complicated than that unfortuantely...although the current nomenclature is more cargo cult than meaningful. I could produce a physically smaller transistor, with a smaller gate, source, and drain. However, depending on the limitations of my process changes for scaling I may not actually be able to pack transistors more tightly. Notionally, the smaller transistor could use less energy which improves the chip design, but not be packed more tightly. There is more than one way to improve a semiconductor at the feature, device, and chip level. The node naming is a useful convention for the industry because saying something like '10nm' efficiently communicates historical context, likely technological changes, timelines, and other things that have nothing to do with the physical size of the devices on the chips. It's basically a form of controlled vocabulary.
- kuprel 6y agoThey should quote sqrt(3000) ~ 55nm as the transistor size
- d110af5ccf 6y agoIt's a bit more complicated than just a single per-area metric. See (https://ieeexplore.ieee.org/abstract/document/9150552 https://ieeexplore.ieee.org/abstract/document/9150552) for an overview.