5 ms·
Suppose you had enough registers, ie. so many that there's no real reason to compilers to save. In that case, you could "support" out-of-order execution by addi
by Arnt 6y ago
Suppose you had enough registers, ie. so many that there's no real reason to compilers to save. In that case, you could "support" out-of-order execution by adding a couple sentences to the compiler guidance documentation for your CPU, telling them that they'll get better performance on o-o-o cores if they wait as long as practical with reusing registers.
- CalChris 6y agoThey've tried variations of this. It takes instruction bits to describe these registers: 32 regs is 5 bits, target + src1 + src2 is 15 bits already. They've tried scratch pads. The Mill CPU's Belt is yet another approach. https://en.wikipedia.org/wiki/Scratchpad_memory https://millcomputing.com/ How to Use 1000 Registers https://caltechconf.library.caltech.edu/200/ 1000 registers would be 10 bits. So they tried register windows. These are all good ideas but they get to compete. So far, I'm a huge AArch64 fan but I now see the purpose of RISC-V. I watched Chris Lattner's ASPLOS talk and it finally clicked. https://www.youtube.com/watch?v=4HgShra-KnY
- Arnt 6y agoI know... and it's quite interesting really, but for the purpose of this thread, I think it's safe to say that the CPU-wallahs spend considerable effort on ways to lighten or avoid register pressure, and from that I infer that all of the currently widely used CPUs do have significant pressure. Much more on the x86 than on sane architectures, of course.