Good comment except this: > 3. AMD64 is basically internally a RISC. They decode some rarely used instructions into multiple micro-ops, but these micro-ops ca

Good comment except this: > 3. AMD64 is basically internally a RISC. They decode some rarely used instructions into multiple micro-ops, but these micro-ops can be very complex still. Example: vfmadd231ps ymm1, ymm2, ymmword ptr [rsi + 4*rcx + 96] The above instruction computes quite a lot of stuff (first the read address, then 8-wide multiply+add), yet on most modern CPUs including AMD Zen 2 it decodes into a single micro-op. More often the opposite happens, AMD64 instructions are merged into a single micro-op, this is called macro-op fusion.