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Also, isn't x86 ISA just a translation layer today? I thought on the metal, there is a RISC like architecture these days anyway.
by lofi_lory 5y ago
Also, isn't x86 ISA just a translation layer today? I thought on the metal, there is a RISC like architecture these days anyway.
- nonameiguess 5y agoIn most cases, yes, but it doesn't get rid of the complexity for compiler backends that can't directly target the real instruction sets Intel uses and have to target the compatibility shim layer instead.
- astrange 5y agoNot really, because the variable length instructions have consequences - mostly good ones because they fit in memory better. Also, the complex memory operands can be executed directly because you can add more ALUs inside the load/store unit. ARM also has more types of memory operands than a traditional RISC (which was just whatever MIPS did.)
- k__ 5y agoI had the impression that M1 would outperform others because it didn't had variable length instructions. Why do you think they have good conequences?
- kalleboo 5y agoI've understood it, the tradeoff is The upside to variable length instructions is that they are on average shorter so you can fit more into your limited cache and you make better use of your RAM bandwidth. The downside is that your decoder gets way more complex. By having a simpler decoder Apple instead has more of them (8 wide decode) and a big reorder buffer to keep them filled. Supposedly Apple solved the downside by simply throwing lots of cache at the problem and putting the RAM on-chip. I'm not a CPU guy and this is what I've gathered from various discussions so I'm happy to be corrected.