I gave it as an example of one way it can complicate a higher perf design, and why it's stuck on new ISAs. There's a lot of choices old school RISC made that h

I gave it as an example of one way it can complicate a higher perf design, and why it's stuck on new ISAs. There's a lot of choices old school RISC made that happen to still be valid at much higher gate counts, but for different reasons. Three address is one of those. "Why do we still have it?" is the more interesting question compared to "why did we do it in the first place" IMO. You can see CISC archs hacking in the "xor REG" instruction as 'erase dependency in OoO hardware' to get around the dependency issues I talked about. Three address doesn't have that root issue because you can always specify a destination that wasn't a source. Additionally, it's not a case of exposing the CISC internal datapath as RISC instructions. CISC vertical microinstructions tend to be two address as well. The horizontal microinstructions can't really be said to have clear source and destination enough to be either two or three address.