3 ms·
Not an expert but I don't think that's quite right. No three-address ISAs (that I know of?) do anything to forbid using one of the sources as a destination, I'm
by wk_end 6y ago
Not an expert but I don't think that's quite right. No three-address ISAs (that I know of?) do anything to forbid using one of the sources as a destination, I'm not even aware of a microarch that punishes you for doing so, and the three-address design goes back to the original RISC/MIPS designs where any sort of advanced dependency analysis in the pipeline wasn't even a consideration (it was considered somewhat un-RISC-y maybe even).
I think the motivation was something more like: there's room in the instruction encoding and it's more flexible. Like you can do things like move a value from one register to another using an `add` instruction instead of a dedicated `move` by using `dest = source + zero`. Internally I think some CPUs were doing that sort of thing anyway to simplify the datapath, and the basic point of RISC was to expose the microarch in the instruction set.
- monocasa 6y agoI gave it as an example of one way it can complicate a higher perf design, and why it's stuck on new ISAs. There's a lot of choices old school RISC made that happen to still be valid at much higher gate counts, but for different reasons. Three address is one of those. "Why do we still have it?" is the more interesting question compared to "why did we do it in the first place" IMO. You can see CISC archs hacking in the "xor REG" instruction as 'erase dependency in OoO hardware' to get around the dependency issues I talked about. Three address doesn't have that root issue because you can always specify a destination that wasn't a source. Additionally, it's not a case of exposing the CISC internal datapath as RISC instructions. CISC vertical microinstructions tend to be two address as well. The horizontal microinstructions can't really be said to have clear source and destination enough to be either two or three address.