3 ms·

Good article, but please don't use defparam!

• tverbeure 5y ago
  This was just a cut-and-paste from an Intel example. But any strong reason why? Do you prefer specifying the params as part of the module instantiation itself?
  • evancox100 5y ago
    Yes, use the #(...) syntax. This has been around since Verilog 2001 and is universally supported. defparam has been deprecated and "might be removed from future versions of the language" (section 23.10.1 of SystemVerilog 2017 spec). They would never actually do this since breaking backwards compatibility is anathema to the industry, but it's not the best thing to use if you can avoid it. One of the main problems with defparam is that you can redefine anything anywhere. The SystemVerilog spec (weirdly) touts this as a benefit: "The defparam statement is particularly useful for grouping all of the parameter value override assignments in one module". Then gives an example that would strike fear into the heart of both verification AND design engineer, where a lone "annotate" module with just defparams redefines the parameters at multiple levels of a completely unrelated hierarchy of other modules. In reality chip designs are so much larger these days that it would be information overload to try to define ever parameter in a single module that you would have to update any time the hierarchy anywhere in your chip changed. It is just such a nonstarter, it's kind of astounding that statement is still in there. It probably dates back to the introduction of the feature.
    • tverbeure 5y ago
      Fixed in the blog post and the example project. Thanks!