I think the apparent increase in Verilog popularity is due to pretty much all FOSS toolchains (i.e. mostly Yosys) only supporting Verilog [1], so most of the co

I think the apparent increase in Verilog popularity is due to pretty much all FOSS toolchains (i.e. mostly Yosys) only supporting Verilog [1], so most of the content publicly visible on blogs etc. uses Verilog. And I guess the reason that most tooling focuses on Verilog is that the VHDL standard is a little bit of a mess from a parsing point of view. Essentially, in order to correctly parse some VHDL file A you first need to parse every other file that A might depend on. [2] Source: Tried writing a VHDL parser a few years ago. [1] AFAIK you can buy a license for a VHDL frontend from one of the companies contributing to Yosys, but that's a different story. [2] Example: What is f(1)? It could be a) calling a function called f with a parameter_association_list consisting of 1 or b) an indexed name, accessing an array called f at index 1, or c) some other things if we're not currently in an expression context. The only way to parse this correctly is to know what f is, but if f is not defined in the file you're currently parsing, there's no way to know other than parsing all other files...