3 ms·
> RISC has only a handful of instructions, that all take 1 clock cycle (with pipelining). This isn't really the case with modern ARM. Fundamentally modern ARM
by enragedcacti 6y ago
> RISC has only a handful of instructions, that all take 1 clock cycle (with pipelining).
This isn't really the case with modern ARM. Fundamentally modern ARM and x86 CPUs are designed very similarly once you get past the instruction decoder. Both 'compile' instructions down to micro-ops that are then executed rather than executing the instruction set directly so the distinctions between the instruction sets themselves don't matter all that much past that point.
The main advantages for ARM come from the decode stage and from larger architectural differences such as relaxed memory ordering requirements.
https://retrocomputing.stackexchange.com/questions/13480/did-any-risc-cpu-ever-take-more-than-one-clock-cycle-per-instruction/13482 https://retrocomputing.stackexchange.com/questions/13480/did...
- fireattack 6y agoSo ARM nowadays is just straightly better than x86?
- enragedcacti 6y agoFor the most part I think so. The main advantages x86 has are based on code size. Many common instructions are 1 or 2 bytes so the executable size on x86 can often be smaller (and more instructions can fit in the instruction cache). I'm sure there are tons of other small differences that weigh in but I'm not well versed enough to know of them.
- hajile 6y agoA paper I read a few months ago compared instruction density between a few different ISAs. Thumb was 15% denser and aarch64 was around 15% less dense compared to x86. Unfortunately, mode switching in thumb impacts performance which is why they dropped it. RISCV compressed instructions are interesting in that they offer the same compact code as thumb, but without the switching penalty (internally, they are expanded in place to normal 32-bit instructions before execution). If they added some dedicated instructions in place of some fused ones, that density could probably increase even more (I say probably because two 16-bit instructions can equal one 32-bit dedicated instruction in a lot of those cases). It’ll be interesting to see what happens when they start designing high performance chips in the near future.