5 ms·

The CPU microarchitecture is truly a quantum leap ahead of x86 processors. The fixed-width nature of arm instructions means there's way more front-end bandwidth

by titzer 6y ago

The CPU microarchitecture is truly a quantum leap ahead of x86 processors. The fixed-width nature of arm instructions means there's way more front-end bandwidth for decode, which can then feed a much larger out-of-order engine. Having memory so close is also a huge win. TBH, I don't know what wizardry they have managed to get power consumption so low, but wow. 15W TDP and trouncing desktop processors pulling 12x that power!

wmf 6y ago
Wait till you see AMD put 8 cores in 15W.
- akmarinov 6y ago
  That’s the thing, while we’re waiting on AMD, Apple is already half way through an M2/3
  - cecja 6y ago
    Yeah, if they had something on their hand they wouldn't put the same chip in everything.
  - ben-schaaf 6y ago
    The 4800U came out in March 2020 with 8 cores, 16 threads.
    - deleted 6y ago
      [deleted]
yxhuvud 6y ago
That is the talk yes, but we don't know how much of the actual performance improvements is simply due to the lower process size. And process size is independent of if it is ARM or x86, but instead depends on manufacturers getting production slots in the chip foundries. Currently Apple is hogging up all the production capabilities of the smallest process that TSMC have.
- hajile 6y ago
  TSMC themselves say shrinking from 7nm to 5nm offers either 15% better performance OR 30% lower power. Neither of those would get x86 anywhere close to m1 in either performance or power consumption.
mhh__ 6y ago
microarchitecturally is M1 really a leap? In terms of decoding bandwidth I'm not sure how many instructions it can actually sustain but it's not like it's 10x - M1 is a basically a very wide version of a tried and tested formula rather than a wholely new thing.
- hajile 6y ago
  x86 decoders are massive. They are about the same size as the integer ALUs in current designs. I think it was an Anandtech interview a couple years ago where someone from AMD said that wider decoders were a no go because of the excessive power consumption relative to performance increase. I’m sure they’ve looked into this exact idea many times from many different angles. ARMs all 32-bit instructions make the decoder trivial in comparison. To parallelize 10kb worth of instructions across 8 decoders means read 32 bytes into the decoders, jump 32 more bytes and do it again (yes, it’s slightly more complex than that, but not too much). x86 instructions are 1-15 bytes. How do you split up to ensure minimal overlap and that one decoder isn’t bottlenecking the processor? How do you speed up parsing one byte at a time? uOp cache and some very interesting parsing strategies help (there’s a couple public papers of those topics from x86 designers). They can’t eliminate the waste or latency issues though. What is amazing to me is their efficiency despite the limitations. When you look at their massive 64-core chips and account for all the extra cache, IO, and interconnect necessary, it seems like scaling up the M1 to those levels would result in a less power efficient chip by (20% or so).

by titzer 6y ago

wmf 6y ago

Wait till you see AMD put 8 cores in 15W.

akmarinov 6y ago
That’s the thing, while we’re waiting on AMD, Apple is already half way through an M2/3
- cecja 6y ago
  Yeah, if they had something on their hand they wouldn't put the same chip in everything.
- ben-schaaf 6y ago
  The 4800U came out in March 2020 with 8 cores, 16 threads.
  - deleted 6y ago
    [deleted]

yxhuvud 6y ago

That is the talk yes, but we don't know how much of the actual performance improvements is simply due to the lower process size. And process size is independent of if it is ARM or x86, but instead depends on manufacturers getting production slots in the chip foundries. Currently Apple is hogging up all the production capabilities of the smallest process that TSMC have.

hajile 6y ago
TSMC themselves say shrinking from 7nm to 5nm offers either 15% better performance OR 30% lower power. Neither of those would get x86 anywhere close to m1 in either performance or power consumption.

mhh__ 6y ago

microarchitecturally is M1 really a leap? In terms of decoding bandwidth I'm not sure how many instructions it can actually sustain but it's not like it's 10x - M1 is a basically a very wide version of a tried and tested formula rather than a wholely new thing.

hajile 6y ago
x86 decoders are massive. They are about the same size as the integer ALUs in current designs. I think it was an Anandtech interview a couple years ago where someone from AMD said that wider decoders were a no go because of the excessive power consumption relative to performance increase. I’m sure they’ve looked into this exact idea many times from many different angles. ARMs all 32-bit instructions make the decoder trivial in comparison. To parallelize 10kb worth of instructions across 8 decoders means read 32 bytes into the decoders, jump 32 more bytes and do it again (yes, it’s slightly more complex than that, but not too much). x86 instructions are 1-15 bytes. How do you split up to ensure minimal overlap and that one decoder isn’t bottlenecking the processor? How do you speed up parsing one byte at a time? uOp cache and some very interesting parsing strategies help (there’s a couple public papers of those topics from x86 designers). They can’t eliminate the waste or latency issues though. What is amazing to me is their efficiency despite the limitations. When you look at their massive 64-core chips and account for all the extra cache, IO, and interconnect necessary, it seems like scaling up the M1 to those levels would result in a less power efficient chip by (20% or so).