This is the classic definition https://dl.acm.org/doi/10.1109/12.4607 https://dl.acm.org/doi/10.1109/12.4607 "An interrupt is precise if the saved process sta

This is the classic definition https://dl.acm.org/doi/10.1109/12.4607 https://dl.acm.org/doi/10.1109/12.4607 "An interrupt is precise if the saved process state corresponds to a sequential model of program execution in which one instruction completes before the next begins. In a pipelined processor, precise interrupts are difficult to implement because an instruction may be initiated before its predecessors have completed."