Due to how the instruction set evolved, for the Intel x86 architecture, you have to look at a lot of bits of the instruction stream to determine where the next

Due to how the instruction set evolved, for the Intel x86 architecture, you have to look at a lot of bits of the instruction stream to determine where the next instruction starts. To execute multiple instructions per clock cycles you also have to decode instruction multiple instructions per clock cycle. I think this old Intel patent talks about one of their decoder implementations: https://patents.google.com/patent/US5758116A/en https://patents.google.com/patent/US5758116A/en