3 ms·

Could you elaborate - what is about the Intel design that makes the decode so inefficient? Is "2b" bits here? Are there examples of ISA or chips that handle va

• Symmetry 6y ago
  Intel x86 isn't self synchonizing. In theory you have to decode every byte of the instruction stream that came before to be sure where the boundaries of an instruction are. Normally it stabilizes after a while in real world instruction streams but you can craft malicious instruction streams which yield two different valid sets of instructions depending on whether you start reading them at an offset or not. Contrast that to something like utf8 where that isn't possible.
  • saagarjha 6y ago
    Note that random x86 code is usually “eventually self-synchronizing”, which id useful if you’re trying to disassemble a blob at a random offset.
• pkaye 6y ago
  Due to how the instruction set evolved, for the Intel x86 architecture, you have to look at a lot of bits of the instruction stream to determine where the next instruction starts. To execute multiple instructions per clock cycles you also have to decode instruction multiple instructions per clock cycle. I think this old Intel patent talks about one of their decoder implementations: https://patents.google.com/patent/US5758116A/en https://patents.google.com/patent/US5758116A/en