Very good summary. One example of such an head ache would be the branch delay slot. It works really well if you have the compiler perform an reorder of instruc

Very good summary. One example of such an head ache would be the branch delay slot. It works really well if you have the compiler perform an reorder of instructions for you so the chip can do more while waiting for memory. In a modern pipeline CPU with register renaming, out of order execution this ISA level reordering would be at best complicating the implementation. The branch delay slot makes sense where you aim to wait 1-3 cycles for memory loads but becomes a meaningless complication in the face of 10's or 100's of cycles waiting for memory seen on high clocked CPUs today.