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SH processors are very good contenders in their specific gate count niche, but have a lot of headaches for implementing higher performance cores that RISC-V was
by monocasa 6y ago
SH processors are very good contenders in their specific gate count niche, but have a lot of headaches for implementing higher performance cores that RISC-V was attempting to explicitly address. A lot of exposed pipeline kind of stuff. Only specified a soft fill TLB. The ISA is very constrained by being 16-bit only that gets in the way of density when compared to other more modern instruction bandwidth conscious RISCs (although it can't be stated enough how much SH inspired all of the later examples, including Thumb and RV-C).
Additionally SH variants with full MMUs would have lost their patent protection after RISC-V was already released and gaining steam.
- freemint 6y agoVery good summary. One example of such an head ache would be the branch delay slot. It works really well if you have the compiler perform an reorder of instructions for you so the chip can do more while waiting for memory. In a modern pipeline CPU with register renaming, out of order execution this ISA level reordering would be at best complicating the implementation. The branch delay slot makes sense where you aim to wait 1-3 cycles for memory loads but becomes a meaningless complication in the face of 10's or 100's of cycles waiting for memory seen on high clocked CPUs today.