3 ms·
Notice that it does not implement an MMU, nor was 64-bit ever implemented in the instruction set.
by chasil 6y ago
Notice that it does not implement an MMU, nor was 64-bit ever implemented in the instruction set.
- yjftsjthsd-h 6y ago> J2 is a nommu processor because sh2 (the processor in the Sega Saturn game console) was, and the last sh2 patent expired in October 2014. The sh4 processor (dreamcast) has an mmu, but the last sh4 patents don't exire until 2016. (Update: we're probably implementing a simpler MMU design which will run the same userspace software but require kernel and QEMU updates, which we'll submit upstream when ready.) Seems like it was in the pipeline, and still should be easier to add an MMU to a fully-fleshed system than create a whole new ISA. For that matter, there are plenty of RISC-V implementations without MMUs, aren't there? So they should be exactly the same. The 64-bit thing I'll give you, although it isn't obvious to me how much that would matter for most places where people are using ARM or RISC-V so far; it limits you to 4G of memory, but in embedded uses (phones, routers, raspberry pi) who cares?