I have an "I2C" (no clock wire necessary, but it's present) bus with 512 WS2811 devices split evenly across a 1:4 fan-out power and signal integrity multiplexer

I have an "I2C" (no clock wire necessary, but it's present) bus with 512 WS2811 devices split evenly across a 1:4 fan-out power and signal integrity multiplexer. This is because I couldn't get 384 devices to maintain signal integrity (only about 340), likely due to too much load on the bus or reflections. 256 devices worked fine. Clocked buses, especially large parallel clocked buses, are generally a bad idea due to clock skew (clock and data signals getting farther out-of-sync with different wire length and loads.)