Matrix multiplication. They use a cascaded Mach-Zhender MEMs array as their systolic matrix multiplier. These types of schemes are limited to the amount of l

Matrix multiplication. They use a cascaded Mach-Zhender MEMs array as their systolic matrix multiplier. These types of schemes are limited to the amount of loss that they have. Additionally since these are analog components they have a certain physical size which is difficult to reduce. In my view this type of architecture does not scale very well.