The last paragraph mentions a single bus (instead of tiles), so they can use a bus sniffing cache coherence protocol (MOESI etc). No problem here. As far as i

The last paragraph mentions a single bus (instead of tiles), so they can use a bus sniffing cache coherence protocol (MOESI etc). No problem here. As far as i know, the frontier is at 60-80 cores, where bus sniffing gets too expensive. However, i'd love to have some references for this.