3 ms·
The major inefficiency I see at the hardware level is the lower amount of work per instruction. This would lead to more data being fetched by the CPU to execute
by michrassena 6y ago
The major inefficiency I see at the hardware level is the lower amount of work per instruction. This would lead to more data being fetched by the CPU to execute (though with one instruction, I suppose you only need the parameters). I'm sure a large cache would mitigate this problem somewhat.