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Sure! I'll keep digging. >D RISC = Reduced Instruction Set Computer. Reduced instructions result in (supposedly) reduced complexity per instruction (which has

Sure! I'll keep digging. >D RISC = Reduced Instruction Set Computer. Reduced instructions result in (supposedly) reduced complexity per instruction (which has failed over time). While each instruction is "simpler" it takes more instructions to accomplish a task. It would stand to reason that it would take more clock cycles to accomplish the same goal on ARM than x86. [1] ARM processors regularly outperform x86 in terms of instructions per cycle. They have to in order to do the same amount of work. That is literally the whole idea of RISC. Simpler instructions executed quickly. [2] But this is not why they are fundamentally not as capable. The reason for that is the pipeline. Or relative lack of pipe-lining. [3] But again, you are comparing a Civic to a Lambo. You have a 3.5w CPU which, per watt, you have the more efficient processor. But that's not good enough. ARM folks love to stand on the efficiency soapbox and preach about performance. You want to have the flexibility of out-of-order execution but don't want to admit the shortcomings that come with it. You have the best performance per watt but you want best overall performance. Which, if you skew every metric in favor of sliced up processors and non-real world benchmarks then sure... Your phone is almost as fast as an entry level laptop when running native code on a single core. If x86 appears slower than ARM it's only because ARM fans have thrown everything but the kitchen sink into their test bench and found the absolute most favorable conditions possible. Anything but admit that their $1200 cell (which was never designed to be faster than your laptop) is "faster per watt per core per thread" than a $150 x86 processor. [1] https://www.androidauthority.com/arm-vs-x86-key-differences-explained-568718/ https://www.androidauthority.com/arm-vs-x86-key-differences-... [2] https://www.extremetech.com/computing/318020-flaw-current-measurements-x86-versus-apple-m1-performance https://www.extremetech.com/computing/318020-flaw-current-me... [3] http://www.csbio.unc.edu/mcmillan/Comp411F17/Lecture26.pdf http://www.csbio.unc.edu/mcmillan/Comp411F17/Lecture26.pdf

tremon 6y ago
All current Intel/AMD processors (since Intel Core/AMD K6) are RISC cores with a complex instruction decoder in front of them. There's more to a processor core than the instruction set, and both pipelining and out-of-order execution have nothing to do with the instruction set architecture. There have been in-order x86 processors (Transmeta and Via, Intel before the Pentium Pro), and there are plenty out-of-order RISC processors: POWER4 and up, SPARC T4, RISC-V, many ARM Cortex models.

tremon 6y ago

All current Intel/AMD processors (since Intel Core/AMD K6) are RISC cores with a complex instruction decoder in front of them. There's more to a processor core than the instruction set, and both pipelining and out-of-order execution have nothing to do with the instruction set architecture. There have been in-order x86 processors (Transmeta and Via, Intel before the Pentium Pro), and there are plenty out-of-order RISC processors: POWER4 and up, SPARC T4, RISC-V, many ARM Cortex models.