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What I don't understand is: ASML is building these machines for making ICs. Why can TSMC use them for 7nm but Intel can only use them for 10 right now? Doesn't

What I don't understand is: ASML is building these machines for making ICs. Why can TSMC use them for 7nm but Intel can only use them for 10 right now? Doesn't ASML make the lenses as well so that you're "only" stuck making the etching thingy (forgot what it's called, but the reflective template of a CPU). It seems like nobody is talking about this, could anyone shine some light?

dragontamer 6y ago
Consider that the wavelength of red light is 700 nm, and the wavelength of UV-C is 100nm to 280nm. And immediately, we see the problem about dropping to 10nm: that's literally smaller than the distance that photons vibrate on their way to the final target. And yeah, 10nm and 7nm is a marketing term, but that doesn't change the fact that these processes are all smaller than the wavelength of light. ------- So there are two ways to get around this problem. 1. Use smaller light: "Extreme UV" is even smaller than normal UV at 13.5nm. Kind of the obvious solution, but higher energy and changes the chemistry slightly, since the light is a different color. Things are getting mighty close to literal "X-Ray Lasers" as they are, so the power requirements are getting quite substantial. 2. Multipatterning -- Instead of developing the entire thing in one shot, do it in multiple shots, and "carefully line up" the chips between different shots. As difficult as it sounds, its been done before at 40nm and other processes. (https://en.wikipedia.org/wiki/Multiple_patterning#EUV_Multiple_Patterning_Possibilities https://en.wikipedia.org/wiki/Multiple_patterning#EUV_Multip...) 3. Do both at the same time to reach 5nm, 4nm, or 3nm. Either way, 10nm and 7nm is the point where the various companies had to decide to do #1 first or #2 first. Either way, your company needs to learn to do both in the long term. TSMC and Samsung went with #1 EUV, and I think Intel though that #2 multi-patterning would be easier. And the rest is history. Seems like EUV was easier after all, and TSMC / Samsung's bets paid off. Mind you, I barely know any of the stuff I'm talking about. I'm not a physicist or chemist. But the above is my general understanding of the issues. I'm sure Intel had their reasons to believe why multipatterning would be easier. Maybe it was easier, but other company issues drove away engineers and something unrelated caused Intel to fall behind.
- carlhjerpe 6y ago
  Thanks, the multipattering choice was an interesting thing to take home regarding why X is ahead of Y.
- labcomputer 6y ago
  Could you not simply take the 2D fourier transform of the desired on-chip pattern and use that as the mask? It seems like the diffraction pattern of the "long" wave laser would give you exactly what you want on the chip... and if you are putting hundreds of chips on a single wafer, it seems like you might not even need to worry too much about ringing at the edges.
  - HelloNurse 6y ago
    You might be confusing the somewhat similar shapes arising from the Fourier transform of step functions etc. or from diffraction from an individual hole or obstacle. Unlike the Fourier transform, which is a purely mathematical operation, diffraction has no "inverse": if you add more diffraction you just add more waves to the projected pattern. The only ways to defeat diffraction are reducing it with shorter wavelengths and compensating it with multiple exposures with different patterns in which light and dark fringes compensate each other: exactly the two general approaches (EUV and multipatterning) taken by the semiconductor industry.
    - labcomputer 6y ago
      I don't think I am, actually. In the far field with a narrow bandwidth coherent light source (i.e., a laser), the projected image should be the FT of the aperture. That limiting condition is sometimes known as Fraunhofer diffraction, and generalizes to arbitrary apertures (not just a single hole). Consider a narrow-band laser incident upon a diffraction grating for example. It produces a single point (well, two or three points, mirrored across the grating), not the uniform smudge that you'd expect by naively adding up the diffraction patterns of a bunch of slits. You should actually try this experiment for yourself! The only trick is that you need a collimated laser and you need it to illuminate the entire inverse-FT-chip-grating aperture at once. This deck has some nice examples of multi-hole apertures on slides 20 and 22: https://www.brown.edu/research/labs/mittleman/sites/brown.edu.research.labs.mittleman/files/uploads/lecture30_0.pdf https://www.brown.edu/research/labs/mittleman/sites/brown.ed...
vzidex 6y ago
I'll take a crack at it, though I'm only in undergrad (took a course on VLSI this semester). Making a device at a specific technology node (e.g. 14nm, 10nm, 7nm) isn't just about the lithography, although litho is crucial too. In effect, lithography is what allows you to "draw" patterns onto a wafer, but then you still need to do various things to that patterned wafer (deposition, etching, polishing, cleaning, etc.). Going from "we have litho machines capable of X nm spacing" to "we can manufacture a CPU on this node at scale with good yield" requires a huge amount of low-level design to figure out transistor sizings, spacings, and then how to actually manufacture the designed transistors and gates using the steps listed above.
- carlhjerpe 6y ago
  Thanks, that clarifies it as far as possible for me who don't really know how the full manufacturing process works. Could we simplify this roughly into "ASML makes the machines to shine light at the right nm, foundries makes the Silicon and packages it into an useful device, architecture designers give you the layout to etch" if my mom were to ask?
  - addaon 6y ago
    A few possible corrections, but one interesting one: the output of a foundry is generally known-good dice -- sliced up and tested bits of a silicon wafer. Packaging is done by IC packaging companies, and is really quite an interesting field in its own right. (Many of the foundries do some packaging in house, especially for more exotic approaches like Intel's Foveros, but this is the exception.)
    - carlhjerpe 6y ago
      I would've guessed that they packaged everything inhouse. I'm fascinated by this industry, it's so incredibly omnipresent products, yet "we" know "nothing" about the process of going from "sand" to gigaflops in your machine.
      - 6y ago
mqus 6y ago
TSMCs 7nm is roughly equivalent to intels 10nm, the numbers don't really mean anything (anymore) and are not comparable
datagram 6y ago
Like others have said, the numbers aren't comparable between manufacturers. Here's a neat video where they use an electron microscope to actually compare the transistor sizes for Intel 14nm and AMD 7nm: https://www.youtube.com/watch?v=1kQUXpZpLXI https://www.youtube.com/watch?v=1kQUXpZpLXI
- carlhjerpe 6y ago
  Thank you, this is not what I was looking for though. Even though they're equivalent TSMC was there way before Intel.
erik 6y ago
For one, "7nm" and "10nm" are just marketing names at this point, and don't really correspond to the physical dimensions of anything on the chips produced. Intel 10nm and TSMC 7nm are considered to have very comparable density. TSMC 5nm and is quite ahead though. As to why it's not just a matter of buying a bunch of ASML lithography machines and plugging them in: In addition to what the other replies have noted, there is so much complexity and precision required in a fab. Consider all of the challenges that would be involved with starting with a bunch of industrial robots, and trying to build a fully automated assembly line that manufactures cars. Then scale precision requirements up by many orders of magnitude.

dragontamer 6y ago

Consider that the wavelength of red light is 700 nm, and the wavelength of UV-C is 100nm to 280nm. And immediately, we see the problem about dropping to 10nm: that's literally smaller than the distance that photons vibrate on their way to the final target. And yeah, 10nm and 7nm is a marketing term, but that doesn't change the fact that these processes are all smaller than the wavelength of light. ------- So there are two ways to get around this problem. 1. Use smaller light: "Extreme UV" is even smaller than normal UV at 13.5nm. Kind of the obvious solution, but higher energy and changes the chemistry slightly, since the light is a different color. Things are getting mighty close to literal "X-Ray Lasers" as they are, so the power requirements are getting quite substantial. 2. Multipatterning -- Instead of developing the entire thing in one shot, do it in multiple shots, and "carefully line up" the chips between different shots. As difficult as it sounds, its been done before at 40nm and other processes. (https://en.wikipedia.org/wiki/Multiple_patterning#EUV_Multiple_Patterning_Possibilities https://en.wikipedia.org/wiki/Multiple_patterning#EUV_Multip...) 3. Do both at the same time to reach 5nm, 4nm, or 3nm. Either way, 10nm and 7nm is the point where the various companies had to decide to do #1 first or #2 first. Either way, your company needs to learn to do both in the long term. TSMC and Samsung went with #1 EUV, and I think Intel though that #2 multi-patterning would be easier. And the rest is history. Seems like EUV was easier after all, and TSMC / Samsung's bets paid off. Mind you, I barely know any of the stuff I'm talking about. I'm not a physicist or chemist. But the above is my general understanding of the issues. I'm sure Intel had their reasons to believe why multipatterning would be easier. Maybe it was easier, but other company issues drove away engineers and something unrelated caused Intel to fall behind.

carlhjerpe 6y ago
Thanks, the multipattering choice was an interesting thing to take home regarding why X is ahead of Y.
labcomputer 6y ago
Could you not simply take the 2D fourier transform of the desired on-chip pattern and use that as the mask? It seems like the diffraction pattern of the "long" wave laser would give you exactly what you want on the chip... and if you are putting hundreds of chips on a single wafer, it seems like you might not even need to worry too much about ringing at the edges.
- HelloNurse 6y ago
  You might be confusing the somewhat similar shapes arising from the Fourier transform of step functions etc. or from diffraction from an individual hole or obstacle. Unlike the Fourier transform, which is a purely mathematical operation, diffraction has no "inverse": if you add more diffraction you just add more waves to the projected pattern. The only ways to defeat diffraction are reducing it with shorter wavelengths and compensating it with multiple exposures with different patterns in which light and dark fringes compensate each other: exactly the two general approaches (EUV and multipatterning) taken by the semiconductor industry.
  - labcomputer 6y ago
    I don't think I am, actually. In the far field with a narrow bandwidth coherent light source (i.e., a laser), the projected image should be the FT of the aperture. That limiting condition is sometimes known as Fraunhofer diffraction, and generalizes to arbitrary apertures (not just a single hole). Consider a narrow-band laser incident upon a diffraction grating for example. It produces a single point (well, two or three points, mirrored across the grating), not the uniform smudge that you'd expect by naively adding up the diffraction patterns of a bunch of slits. You should actually try this experiment for yourself! The only trick is that you need a collimated laser and you need it to illuminate the entire inverse-FT-chip-grating aperture at once. This deck has some nice examples of multi-hole apertures on slides 20 and 22: https://www.brown.edu/research/labs/mittleman/sites/brown.edu.research.labs.mittleman/files/uploads/lecture30_0.pdf https://www.brown.edu/research/labs/mittleman/sites/brown.ed...

vzidex 6y ago

I'll take a crack at it, though I'm only in undergrad (took a course on VLSI this semester). Making a device at a specific technology node (e.g. 14nm, 10nm, 7nm) isn't just about the lithography, although litho is crucial too. In effect, lithography is what allows you to "draw" patterns onto a wafer, but then you still need to do various things to that patterned wafer (deposition, etching, polishing, cleaning, etc.). Going from "we have litho machines capable of X nm spacing" to "we can manufacture a CPU on this node at scale with good yield" requires a huge amount of low-level design to figure out transistor sizings, spacings, and then how to actually manufacture the designed transistors and gates using the steps listed above.

carlhjerpe 6y ago
Thanks, that clarifies it as far as possible for me who don't really know how the full manufacturing process works. Could we simplify this roughly into "ASML makes the machines to shine light at the right nm, foundries makes the Silicon and packages it into an useful device, architecture designers give you the layout to etch" if my mom were to ask?
- addaon 6y ago
  A few possible corrections, but one interesting one: the output of a foundry is generally known-good dice -- sliced up and tested bits of a silicon wafer. Packaging is done by IC packaging companies, and is really quite an interesting field in its own right. (Many of the foundries do some packaging in house, especially for more exotic approaches like Intel's Foveros, but this is the exception.)
  - carlhjerpe 6y ago
    I would've guessed that they packaged everything inhouse. I'm fascinated by this industry, it's so incredibly omnipresent products, yet "we" know "nothing" about the process of going from "sand" to gigaflops in your machine.
    - 6y ago

mqus 6y ago

TSMCs 7nm is roughly equivalent to intels 10nm, the numbers don't really mean anything (anymore) and are not comparable

datagram 6y ago

Like others have said, the numbers aren't comparable between manufacturers. Here's a neat video where they use an electron microscope to actually compare the transistor sizes for Intel 14nm and AMD 7nm: https://www.youtube.com/watch?v=1kQUXpZpLXI https://www.youtube.com/watch?v=1kQUXpZpLXI

carlhjerpe 6y ago
Thank you, this is not what I was looking for though. Even though they're equivalent TSMC was there way before Intel.

erik 6y ago

For one, "7nm" and "10nm" are just marketing names at this point, and don't really correspond to the physical dimensions of anything on the chips produced. Intel 10nm and TSMC 7nm are considered to have very comparable density. TSMC 5nm and is quite ahead though. As to why it's not just a matter of buying a bunch of ASML lithography machines and plugging them in: In addition to what the other replies have noted, there is so much complexity and precision required in a fab. Consider all of the challenges that would be involved with starting with a bunch of industrial robots, and trying to build a fully automated assembly line that manufactures cars. Then scale precision requirements up by many orders of magnitude.