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This might be a very dumb question but it always bothered me - silicon wafers are always shown as great circles, but processor dies are obviously square. But i

This might be a very dumb question but it always bothered me - silicon wafers are always shown as great circles, but processor dies are obviously square. But it looks like the etching etc goes right to the circular edges - wouldn't it be better to leave the dead space untouched?

pas 6y ago
I think these are just press/PR wafers and real production ones don't pattern on the edge. (First of all it takes time, and in case of EUV it means things amortize even faster, because every shot damages the "optical elements" a bit.) edit: it also depends on how many dies the mask (reticle) has on it. Intel uses one die reticles, so i. theory their real wafers have no situation in which they have partial dies at the edge.
- dogma1138 6y ago
  Real wafers have the chip patterning going to the edge and this can results and often does in partial dies. There is no reason not too so this and the edges are also often used for calibration and (potentially) destructive testing. The only area of the wafer that will not be exposed is the notch, it’s always on one side of the circle and it’s used for moving the wafer around, this is why you often see wafers with one of the sides cut off giving it the flat tire shape.
w0utert 6y ago
Most semiconductor production processes like etching, doping, polish etc are done on the full wafer, not on individual images/fields. So there is nothing to be gained there in terms of production efficiency. The litho step could in theory be optimized by skipping incomplete fields at the edges, but the reduction in exposure time would be relatively small, especially for smaller designs that fit multiple chips within a single image field. I imagine it would als introduce yield risk because of things like uneven wafer stress & temperature, higher variability in stage move time when stepping edge fields vs center fields, etc.
andromeduck 6y ago
Many of the process steps involve rotation so this is impractical.

pas 6y ago

I think these are just press/PR wafers and real production ones don't pattern on the edge. (First of all it takes time, and in case of EUV it means things amortize even faster, because every shot damages the "optical elements" a bit.) edit: it also depends on how many dies the mask (reticle) has on it. Intel uses one die reticles, so i. theory their real wafers have no situation in which they have partial dies at the edge.

dogma1138 6y ago
Real wafers have the chip patterning going to the edge and this can results and often does in partial dies. There is no reason not too so this and the edges are also often used for calibration and (potentially) destructive testing. The only area of the wafer that will not be exposed is the notch, it’s always on one side of the circle and it’s used for moving the wafer around, this is why you often see wafers with one of the sides cut off giving it the flat tire shape.

w0utert 6y ago

Most semiconductor production processes like etching, doping, polish etc are done on the full wafer, not on individual images/fields. So there is nothing to be gained there in terms of production efficiency. The litho step could in theory be optimized by skipping incomplete fields at the edges, but the reduction in exposure time would be relatively small, especially for smaller designs that fit multiple chips within a single image field. I imagine it would als introduce yield risk because of things like uneven wafer stress & temperature, higher variability in stage move time when stepping edge fields vs center fields, etc.

andromeduck 6y ago

Many of the process steps involve rotation so this is impractical.