4 ms·
From a yield perspective, if core failures are independent events, binning is probably easier with the big chiplet approach. The Epyc 3 approach does have some
by totalZero 6y ago
From a yield perspective, if core failures are independent events, binning is probably easier with the big chiplet approach.
The Epyc 3 approach does have some drawbacks. Looking at the Epyc 3 TDP numbers, there's probably a nontrivial thermal cost to breaking out the dies as AMD has. Not to mention the I/O for Epyc 3 is not on TSMC 7nm.